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| 0 R VirtexTM 2.5 V Field Programmable Gate Arrays 0 3 DS003-1 (v2.5 ) April 2, 2001 Product Specification Features * Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz - 66-MHz PCI Compliant - Hot-swappable for Compact PCI Multi-standard SelectIOTM interfaces - 16 high-performance interface standards - Connects directly to ZBTRAM devices Built-in clock-management circuitry - Four dedicated delay-locked loops (DLLs) for advanced clock control - Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets Hierarchical memory system - LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register - Configurable synchronous dual-ported 4k-bit RAMs - Fast interfaces to external high-performance RAMs Flexible architecture that balances speed and density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode * Supported by FPGA FoundationTM and Alliance Development Systems - Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager - Wide selection of PC and workstation platforms SRAM-based in-system configuration - Unlimited re-programmability - Four programming modes 0.22 mm 5-layer metal process 100% factory tested * * * * * Description The Virtex FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 mm CMOS process. These advances make Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex family comprises the nine members shown in Table 1. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market. * * Table 1: Virtex Field-Programmable Gate Array Family Members Device XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 System Gates 57,906 108,904 164,674 236,666 322,970 468,252 661,111 888,439 1,124,022 CLB Array 16x24 20x30 24x36 28x42 32x48 40x60 48x72 56x84 64x96 Logic Cells 1,728 2,700 3,888 5,292 6,912 10,800 15,552 21,168 27,648 Maximum Available I/O 180 180 260 284 316 404 512 512 512 Block RAM Bits 32,768 40,960 49,152 57,344 65,536 81,920 98,304 114,688 131,072 Maximum SelectRAM+TM Bits 24,576 38,400 55,296 75,264 98,304 153,600 221,184 301,056 393,216 (c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS003-1 (v2.5 ) April 2, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 1 of 4 1 VirtexTM 2.5 V Field Programmable Gate Arrays R Virtex Architecture Virtex devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing resources. The abundance of routing resources permits the Virtex family to accommodate even the largest and most complex designs. Virtex FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. In some modes, the FPGA reads its own configuration data from an external PROM (master serial mode). Otherwise, the configuration data is written into the FPGA (SelectMAPTM, slave serial, and JTAG modes). The standard Xilinx FoundationTM and Alliance SeriesTM Development systems deliver complete design support for Virtex, covering every aspect from behavioral and schematic entry, through simulation, automatic design translation and implementation, to the creation, downloading, and readback of a configuration bit stream. Xilinx thoroughly benchmarked the Virtex family. While performance is design-dependent, many designs operated internally at speeds in excess of 100 MHz and can achieve 200 MHz. Table 2 shows performance data for representative circuits, using worst-case timing parameters. Table 2: Performance for Common Circuit Functions Function Register-to-Register Adder Pipelined Multiplier Address Decoder 16:1 Multiplexer Parity Tree 9 18 36 Chip-to-Chip HSTL Class IV LVTTL,16mA, fast slew 200 MHz 180 MHz 16 64 8x8 16 x 16 16 64 5.0 ns 7.2 ns 5.1 ns 6.0 ns 4.4 ns 6.4 ns 5.4 ns 4.1 ns 5.0 ns 6.9 ns Bits Virtex -6 Higher Performance Virtex devices provide better performance than previous generations of FPGA. Designs can achieve synchronous system clock rates up to 200 MHz including I/O. Virtex inputs and outputs comply fully with PCI specifications, and interfaces can be implemented that operate at 33 MHz or 66 MHz. Additionally, Virtex supports the hot-swapping requirements of Compact PCI. Module 1 of 4 2 www.xilinx.com 1-800-255-7778 DS003-1 (v2.5 ) April 2, 2001 Product Specification R VirtexTM 2.5 V Field Programmable Gate Arrays Virtex Device/Package Combinations and Maximum I/O Table 3: Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) Package CS144 TQ144 PQ240 HQ240 BG256 BG352 BG432 BG560 FG256 FG456 FG676 FG680 176 176 176 260 176 284 312 404 444 512 444 512 512 180 180 180 260 180 260 260 316 316 404 316 404 316 404 404 XCV50 94 98 166 XCV100 94 98 166 166 166 166 166 166 166 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 Virtex Ordering Information Example: Device Type Speed Grade -4 -5 -6 XCV300 -6 PQ 240 C Temperature Range C = Commercial (TJ = 0C to +85C) I = Industrial (TJ = -40C to +100C) Number of Pins Package Type BG = Ball Grid Array FG = Fine-pitch Ball Grid Array PQ = Plastic Quad Flat Pack HQ = High Heat Dissipation QFP TQ = Thin Quad Flat Pack CS = Chip-scale Package Figure 1: Virtex Ordering Information DS003-1 (v2.5 ) April 2, 2001 Product Specification www.xilinx.com 1-800-255-7778 Module 1 of 4 3 VirtexTM 2.5 V Field Programmable Gate Arrays R Revision History Date 11/98 01/99 02/99 05/99 05/99 07/99 Version 1.0 1.2 1.3 1.4 1.5 1.6 Initial Xilinx release. Updated package drawings and specs. Update of package drawings, updated specifications. Addition of package drawings and specifications. Replaced FG 676 & FG680 package drawings. Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, "0" hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE. Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43. Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. Modified "Pins not listed ..." statement. Speed grade update to Final status. Modified Table 18. * * * * * 04/01 2.5 * * Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. Corrected Units column in table under IOB Input Switching Characteristics. Added values to table under CLB SelectRAM Switching Characteristics. Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in Table 18. Corrected BG256 Pin Function Diagram. Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. Converted file to modularized format. See Virtex Data Sheet section. Revision 09/99 1.7 01/00 1.8 01/00 1.9 03/00 05/00 05/00 09/00 2.0 2.1 2.2 2.3 10/00 2.4 Virtex Data Sheet The Virtex Data Sheet contains the following modules: * * DS003-1, Virtex 2.5V FPGAs: Introduction and Ordering Information (Module 1) * * DS003-3, Virtex 2.5V FPGAs: DC and Switching Characteristics (Module 3) DS003-2, Virtex 2.5V FPGAs: Functional Description (Module 2) DS003-4, Virtex 2.5V FPGAs: Pinout Tables (Module 4) Module 1 of 4 4 www.xilinx.com 1-800-255-7778 DS003-1 (v2.5 ) April 2, 2001 Product Specification |
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